A FIFO bu er with real - time interface

The design of a FIFO buuer with fully asynchronous, non-blocking write and read operation is presented. The buuer's logic consists of a standard self-timed FIFO (e.g. pipeline) surrounded by two special interface blocks, In and Out, connected to Writer and Reader, respectively. To avoid temporal blocking of Writer requesting for a write when the pipeline is full the In block implements skipping of the data item. Similarly, if Reader attempts to read an empty pipe, to avoid its blocking, a special acknowledge signal is produced telling Reader to re-read the previous item. These blocks are synthe-sised from their Signal Transition Graph (STG) speciications using an asynchronous circuit synthesis tool, petrify. The proposed solution is compared and contrasted against a previously known four-slot mechanism.